A semiconductor memory apparatus, for example a semiconductor memory module, includes a plurality of semiconductor memory units on a board which communicate with a control unit by means of different buses. FIG. 1 shows a top side of a semiconductor memory module 1, for example a buffered DIMM (Dual In-Line Memory Module), in which semiconductor memory units P1, . . . , P18 are arranged in a plurality of rows R1, R2, R3 and R4 to form a left-hand side L and a right-hand side R of a control unit SB. The control unit SB is positioned in the center of the board MP. In the case of a semiconductor memory module in the configuration 8R×4, the top side and underside of the module board respectively hold 36 memory units. Each of the memory units contains two memory chips in a stacked arrangement (dual stack), so that the memory module has a total of 144 memory chips.
FIG. 2 shows a simplified illustration of a memory chip 100a. The memory chip 100a comprises a memory cell array 10 which contains memory cells SZ along word lines WL and bit lines BL. In the case of DRAM (Dynamic Random Access Memory) memory cells, a memory cell has a selection transistor AT and a storage capacitor SC. In order to select one of the memory cells in the memory cell array 10, address signals are applied to an address connection A100 which is connected to an address register 30. In order to control read or write access operations, control signals are applied to a control connection S100 which is connected to a control circuit 20. For read access, the memory chip produces data which have been read from the memory cell array on a data connection D100. In the case of write access, the data connection D100 has data applied to it which are written to the memory cell array. The read and write access operations take place in sync with a clock signal which is applied to a clock connection C100 of the memory chip.
In order to control memory access operations, the memory chip is actuated by the control unit with the control/address signals via a control/address bus, known as the CA (Command Address) bus, and with the clock signal via a clock bus, known as the CLK bus.
It is desirable to provide a memory module with a suitable configuration or arrangement of CA and CLK buses connected with respective memory units that provides suitable signal integrity of the clock signal during read and write operations of the memory module.